WORK EXPERIENCE
ARTERIS
Chief Operating Officer (Mar 2021 - Present) Campbell, CA
QUALCOMM
VP, Engineering (Nov 2017 - Mar 2021) Santa Clara, CA
Senior Director, Technology (Oct 2013 – Nov 2017) Santa Clara, CA
Following the acquisition of Arteris engineering assets, assembled, grew and managed the SoC Infrastructure IP team, a ~500-people organization distributed across the US, India, France and Ireland, responsible for the development and deployment of Infrastructure IP for all Snapdragon mobile SoCs and many other SoCs across Qualcomm. IPs include interconnects, coherent interconnects, SMMUs, system caches, DDR subsystems, power, clocking, debug and other smaller IPs. The team is fully integrated, from architecture and performance to design, verification, implementation, deployment and post-silicon activities.
Created and successfully deployed a broad roadmap covering the needs of very different SoCs using a blend of different IPs across tiers and markets, including off-the-shelf IPs.
Standardized the use of the interconnect IP across SoCs and IP subsystems, enabling a very dynamic mobile SoC roadmap with extremely fast development cycles and very high productivity.
ARTERIS
Chief Technical Officer (Jul 2011 - Oct 2013) Sunnyvale, CA
Qualcomm acquired "certain technology assets" of Arteris in Oct 2013.
Joined the Arteris team to expand the interconnect product portfolio and acquire new customers. Worked on the development of interconnect IP extensions related to cache coherency, last-level caches, SMMU integration and PCI-ordered networks.
Worked with the architecture teams of many leading SoC vendors to deploy Arteris products and develop new features and IPs.
Led the expansion of the patent portfolio.
NVIDIA
Senior Architecture Manager (Apr 2008 - Jul 2011) Santa Clara, CA
Principal Architect
Architecture lead/manager of the Tegra 4 SoC. System architect on other Tegra SoCs including Tegra K1 and lead SoC architect on the early development of the Denver custom CPU.
Specific contributions include system backbones, memory subsystem, CPU interfacing, buses, address maps, clocking, power management.
MONTALVO SYSTEMS
Chief SoC Architect (Jul 2005 - Apr 2008) Santa Clara, CA
This was a complex multi-core x86 design targeted at the notebook market.
I was responsible for the architecture (and microarchitecture) of most of the chip outside the cores and caches. This included the memory controller, the I/O interfaces, the power management subsystem, power and clocking domains/schemes and the various analog and miscellaneous functions (interrupt controllers, PLLs, efuses, temperature sensors, JTAG...). I was also responsible for many global functions like address mapping, reset/power management, register accesses... and helped on many cache- and core-related issues.
Finally, I was responsible for the technical interactions with our chipset partner.
SIBYTE / BROADCOM
Senior Principal Scientist, Broadcom (Dec 2000 - Jul 2005) Santa Clara, CA
Design Engineer, SiByte (Sep 2000 - Dec 2000) Santa Clara, CA
SiByte was acquired by Broadcom in Dec 2000.
Lead SoC architect of the Broadcom SiByte™ BCM1255/BCM1280/BCM1455/BCM1480 (Broadcom, FPF), winner of the Microprocessor Report 2004 High-Performance Embedded Processor Award (Broadcom). This was a family of dual- and quad-core GHz-class MIPS64 highly integrated System-on-a-Chip devices with a variety I/O interfaces (DDR/DDR2, HyperTransport, PCI-X, SPI-4, Gigabit Ethernet...) and internal engines (2x32-channel packet DMA engine, ccNUMA controller, Data Mover...).
In the pre-tapeout phase, I was responsible for the specifications (User Manual, Datasheet), part of the architecture and micro-architecture and was involved in a number of collateral activities (customer discussions, IP blocks, packaging...). In the post-tapeout phase, I worked on customer support, silicon debug, bug tracking, revision and new feature planning... The chips starting sampling in 4Q04.
DIGITAL EQUIPMENT CORPORATION / COMPAQ
Member of the research staff, Systems Research Center (Sep 1997 - Sep 2000) Palo Alto, CA
Digital was acquired by Compaq in May 1998.
Custom compositing infrastructure for Distributed 3D rendering using off-the-shelf graphics cards and a custom interconnect: Architected and implemented Sepia (1 and 2), a scalable 3D compositing infrastructure based on Compaq's ServerNet networking product. Architected and helped design Sepia 2, a custom PCI 66/64 FPGA+networking board (photo). Developed all the low-level software runtime, FPGA code, verification and test software and OpenGL-based demonstrations.
Developed many of the PCI Pamette (photo) applications and utilities. Also ported and maintained all the PCI Pamette environment from Digital Unix to Windows NT, including the device driver.
Implemented an IDE disk interface on a custom board (photo). The interface looks like an IDE disk on one side, and is interfaced through a PCI bus to an embedded processor. The hardware part is implemented on an FPGA. Wrote both the hardware and software code to support the ATA specification. Also implemented a prototype of the IDE interface on PCI Pamette.
Used a simple PCI bus spy application on PCI Pamette to acquire information on the maximum PCI bandwidth attainable on a given system, and also to help debugging or profiling existing PCI devices in system, without interference. Measured PCI performance and real-time capabilities (interrupt dispatching time) of many x86- and Alpha-based system running Windows NT and Digital Unix.
OTHERS
Intern, Systems Research Center, Digital Equipment Corporation (Jun 1996 - Sep 1996) Palo Alto, CA
Implemented part of the head-end add-on board of a cable modem on PCI Pamette FPGA-based board.
Full-time research and teaching assistant, Pôle Universitaire Léonard de Vinci (Sep 1995 - Sep 1997) France
Developed a fast camera interface for the Swedish Vacuum Solar Telescope, Canary Islands. Improved the response time and the robustness of a 60 Hz, 20 MB/s CCD camera interface implemented on a TURBOChannel Pamette (FPGA-based board). Added Real-Time control for polarizing LCD devices.
Intern, Paris Research Laboratory, Digital Equipment Corporation, Paris, France and CERN, Geneva, Switzerland (Feb 1994 - Sep 1994)
Designed and implemented 2 High-Energy Physics particle tracking algorithms for the Large Hadron Collider at CERN on the DECPeRLe-1 FPGA-based reconfigurable board. Achieved best performance compared to a variety of other architectures, e.g. 500x to 1000x the speed of the software implementations.
Intern, Centre de Mathématiques Appliquées, Ecole des Mines de Paris (1993) Sophia-Antipolis, France.
Implemented an algorithm of stereovision (based on local correlation, developed at INRIA) on the DECPeRLe-1 FPGA-based reconfigurable board. Achieved speedups of 35x compared to a 4-DSP board and 200x compared to a Sparc 2 workstation, which made it the first real-time implementation of this family of algorithms. This was also probably the first application ever using run-time reconfiguration of FPGAs.
EDUCATION
1995-1997: PhD in Computer Science, Ecole Polytechnique on "Applications of Programmable Active Memories".
1993-1995: Master of Science in Theoretical Computer Science ("DEA Informatique Mathématiques et Applications" - Ecole Polytechnique, Ecole Normale Supérieure, University of Paris VI, VII and XI).
1993-1995: Engineering Degree, Ecole Nationale Supérieure des Télécommunications de Paris. Majors: Electronics and Computer Science. Thesis in Digital Electronics.
1990-1993: Engineering Degree, Ecole Polytechnique. Majors: Algebra and Computer Science and Theoretical Computer Science and Applications.
PUBLICATIONS AND PATENTS
I am a named inventor on more than 60 issued US patents (USPTO).
From 1993 to 2004, I also authored a number of conference and journal papers (full list).